Senior Circuit Timing Engineer

Job Description:

• Participate in groundbreaking processor design in deep submicron technologies
• Design innovative circuits for hardware security, adaptive clocking, and power management solutions
• Drive timing analysis and signoff of custom circuit macros, including digital, semi-custom, and analog mixed-signal
• Validate timing using STA tools including Nanotime, PrimeTime, Tempus, and SPICE simulation tools
• Collaborate with cross-functional teams to improve power, performance, area, and reliability of next-generation products
• Develop timing models and methodology for innovative custom macro designs
• Perform transistor-level circuit design and timing, schematic entry, and layout delivery
• Integrate AI/ML techniques into the design process and methodology
• Work with PD, DFX, Clocks, and other teams on timing signoff strategy, timing constraints, timing and power convergence, DFT, and timing ECO implementation

Requirements:

• BSEE/MS preferred in Electrical, Computer Engineering or equivalent experience
• 6+ years of digital circuit design experience for Masters and 8+ years for Bachelors
• Excellent understanding of deep submicron process issues and digital circuit design techniques
• Expertise in industry standard STA tools such as Nanotime, Primetime, Tempus, and other timing analysis tools
• Hands-on experience running SPICE simulations, EM/IR analysis, and static timing analysis/closure
• Proven experience in timing constraints generation and management
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and glitch noise
• Solid understanding of extracted timing models and usage of .libs in Primetime
• Knowledge of process variation effect modeling and design convergence in multi-GHz deep submicron technology
• Proven ownership and hands-on experience across the entire silicon design flow, from micro-architecture and RTL design to back-end execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA, and PVerf
• Proven capability in post-silicon characterization and debug
• Track record of independently driving and delivering complex features from conception through tape-out and validation
• Knowledge of timing closure strategies for digital logic/macros part of AMS designs/IPs

Benefits:

• Equity
• Benefits